diff --git a/target/i386/translate.c b/target/i386/translate.c
index 77d6b73e42..f8ff743acf 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -6716,23 +6716,39 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
             gen_eob(s);
         }
         break;
-    case 0x9e: /* sahf */
+    case 0x9e: { /* sahf */
         if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
             goto illegal_op;
+#ifdef TARGET_X86_64
+        int bak = s->x86_64_hregs;
+        s->x86_64_hregs = 0;
+#endif
         gen_op_mov_v_reg(s, MO_8, s->T0, R_AH);
+#ifdef TARGET_X86_64
+        s->x86_64_hregs = bak;
+#endif
         gen_compute_eflags(s);
         tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
         tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C);
         tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, s->T0);
         break;
-    case 0x9f: /* lahf */
+    }
+    case 0x9f: { /* lahf */
         if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
             goto illegal_op;
         gen_compute_eflags(s);
         /* Note: gen_compute_eflags() only gives the condition codes */
         tcg_gen_ori_tl(s->T0, cpu_cc_src, 0x02);
+#ifdef TARGET_X86_64
+        int bak = s->x86_64_hregs;
+        s->x86_64_hregs = 0;
+#endif
         gen_op_mov_reg_v(s, MO_8, R_AH, s->T0);
+#ifdef TARGET_X86_64
+        s->x86_64_hregs = bak;
+#endif
         break;
+    }
     case 0xf5: /* cmc */
         gen_compute_eflags(s);
         tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);